MACH1 डाटा शीट PDF( Datasheet )

MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x x x x x x x x x x x x x High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCN

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCN

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCN

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic Lattice Semiconductor DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCN

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 High-Density EE CMOS Programmable Logic Lattice Semiconductor DISTINCTIVE CHARACTERISTICS s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD