डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
M15F2G16128A-EFBG2L | DDR3 SDRAM ESMT
DDR3 SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQ |
ESMT |
|
M15F2G16128A-EFBG2L | 16M x 16 Bit x 8 Banks DDR3 SDRAM ESMT
DR3 SDRAM
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Do |
ESMT |
|
M15F2G16128A-EFBG2LS | DDR3 SDRAM ESMT
DDR3 SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQ |
ESMT |
|
M15F2G16128A-EFBG2LS | 16M x 16 Bit x 8 Banks DDR3 SDRAM ESMT
DR3 SDRAM
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Do |
ESMT |
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