डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
HD74HC27 | Triple 3-input NOR Gates HD74HC27
Triple 3-input NOR Gates
Features
• • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input |
Hitachi Semiconductor |
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HD74HC27 | Triple 3-input NOR Gates HD74HC27
Triple 3-input NOR Gates
Features
• High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Cu |
Renesas |
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HD74HC273 | Octal D-type Flip-Flops (with Clear) HD74HC273
Octal D-type Flip-Flops (with Clear)
Description
This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is |
Hitachi Semiconductor |
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HD74HC273 | Octal D-type Flip-Flops HD74HC273
Octal D-type Flip-Flops (with Clear)
REJ03D0604-0300 Rev.3.00
Mar 25, 2009
Description
This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having |
Renesas |
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HD74HC279 | Quad. S-R Latches HD74HC279
Quad. S–R Latches
Description
The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R in |
Hitachi Semiconductor |
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HD74HC279 | Octal D-type Flip-Flops HD74HC279
Octal D-type Flip-Flops (with Clear)
REJ03D0605–0200 (Previous ADE-205-483)
Rev.2.00 Jan 31, 2006
Description
The latch is ideally suited for use as temporary stage for binary information process |
Renesas |
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