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IDT8T53S111I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1:10 LVPECL Output Fanout Buffer - Integrated Device Technology

भाग संख्या IDT8T53S111I
समारोह 1:10 LVPECL Output Fanout Buffer
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT8T53S111I pdf
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 16,
25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
VCC
SEL
PCLK0
nPCLK0
VREF
PCLK1
nPCLK1
VEE
VCCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Type
Power
Input
Pulldown
Input
Input
Pulldown
Pulldown/
Pullup
Output
Input
Input
Power
Pulldown
Pulldown/
Pullup
Description
Power supply pin.
Reference select control. See Table 3 for function. LVCMOS/LVTTL interface
levels.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock input.
Bias voltage generator for the nPCLK[0:1] inputs in single-ended input signal
applications.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock input.
Negative power supply pin.
Power
Output power supply pins.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3A. SEL Input Selection Function Table
Input
SEL
Operation
0 (default) PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
NOTE: SEL is an asynchronous control.
IDT8T53S111NLGI REVISION A JULY 12, 2012
2
©2012 Integrated Device Technology, Inc.

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