IDT82V3910 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - Synchronous Ethernet SETS - Integrated Device Technology

भाग संख्या IDT82V3910
समारोह Synchronous Ethernet SETS
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
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IDT82V3910 pdf
The 82V3910 Synchronous Ethernet (SyncE) SETS meets the
requirements of ITU-T G.8262/G.813 for EEC/SEC options 1 and 2; and
it meets the requirements of Telcordia GR-253-CORE Stratum 3 (S3)
and SONET Minimum Clock (SMC). The 82V3910 ultra-low jitter output
clocks can be used to directly synchronize 10GBASE-R/10GBASE-W
and OC-192/STM-64 PHYs and 40GBASE-R PHYs in Synchronous
Ethernet and SONET/SDH equipment.
The Synchronous Equipment Timing Source (SETS) functions are
provided by two independent digital PLLs (DPLLs), T0 and T4, each with
embedded clock synthesizers. The T0 DPLL meets the network syn-
chronization requirements for frequency accuracy, pull-in, hold-in, pull-
out, noise generation, noise tolerance, transient response and holdover
performance. The T4 DPLL provides rate conversion functions that can
be used, for example, to convert a recovered line clock to a 1.544 MHz,
2.048MHz or 64 kHz synchronization reference for external equipment.
The 82V3910 provides ten single ended reference inputs and two dif-
ferential reference inputs that can operate at common Ethernet, SONET/
SDH and PDH frequencies and other frequencies. The device also pro-
vides two Alternate Mark Inversion (AMI) inputs for Composite Clock
(CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization infor-
mation. The references are continually monitored for loss of signal and
for frequency offset per user programmed thresholds. All of the refer-
ences are available to both digital PLLs (DPLLs). The active reference
for each DPLL is determined by forced selection or by automatic selec-
tion based on user programmed priorities and locking allowances and
based on the reference monitors.
The 82V3910 can accept a clock reference and a phase locked
external sync signal as a pair. The T0 DPLL can lock to the reference
clock input and align its frame sync and multi-frame sync outputs with
the paired external sync input. The device provides to two external sync
inputs that can be associated with any of the twelve reference inputs to
create up to two pairs. The external sync signals can have a frequency
of 1 Hz, 2 kHz or 8 kHz. This feature enables the T0 DPLL to phase
align its frame sync and multi-frame sync outputs with an external sync
input without the need use a low bandwidth setting to lock directly to an
external sync input.
Both DPLLs support four primary operating modes: Free-Run,
Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In
Free-Run mode the DPLLs generate clocks based on the master clock
alone. In Locked mode the DPLLs filter reference clock jitter with the
selected bandwidth. In Locked mode the long-term DPLL frequency
accuracy is the same as the long term frequency accuracy of the
selected input reference. In Holdover mode the DPLL uses frequency
data acquired while in Locked mode to generate accurate frequencies
when input references are not available. In DCO Control Mode the DPLL
control loop is opened and the DCO can be used by an algorithm (e.g.
IEEE 1588 clock servo) running on an external processor to synthesize
clock signals.
The 82V3910 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLLs in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLLs in Free-Run mode and in Holdover mode.
The T0 DPLL can be configured with a range of selectable filtering
bandwidths from 0.5 mHz to 35 Hz. The 15 mHz and lower bandwidths
can be used to lock the T0 DPLL directly to a 1 pulse per second (PPS)
reference. The 0.1 Hz bandwidth can be used for G.8262/G.813 Option
2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths
in the range 1.2 Hz to 8 Hz can be used for G.8262/G.813 Option 1
applications. The bandwidths 18 Hz and 35 Hz can be used in jitter
attenuation and rate conversion applications.
The T4 DPLL can be configured with filtering bandwidths of 18Hz or
35 Hz.
The clocks synthesized by the 82V3910 DPLLs can be passed
through either of the two independent voltage controlled crystal oscillator
(VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drive
two independent dividers that have differential outputs. The APLLs use
external crystal resonators with resonant frequencies equal to the APLL
base frequency divided by 25. Both APLLs can be provisioned with one
or two selectable crystal resonators to support up to two base frequen-
cies per APLL. The output clocks generated by the APLLs exhibit jitter
below 0.30ps RMS over the integration range 10 kHz to 20 MHz for most
output frequencies.
Any of the 82V3910 DPLL clocks can be routed through a mux to any
of five single ended outputs via independent output dividers. The output
of the T0 DPLL can be routed through the two auto-dividers to the single
ended frame sync output that operates at 8 kHz or 1 PPS,
Description 2 July 1, 2013

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भाग संख्याविवरणविनिर्माण
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