IDT82V3396 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - Dual Synchronous Ethernet Line Card PLL - Integrated Device Technology

भाग संख्या IDT82V3396
समारोह Dual Synchronous Ethernet Line Card PLL
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
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IDT82V3396 pdf
The IDT82V3396 Dual Synchronous Ethernet Line Card PLL is used
to synchronize line cards in Synchronous Ethernet and SONET/SDH
equipment, and in wireless base stations. The two independent timing
paths allow the device to simultaneously synchronize transmit interfaces
with the selected system backplane clock, and provide a recovered
clock from a selected receive interface to the system backplane.
The IDT82V3396 accepts up to 6 input references operating at com-
mon Ethernet, SONET/SDH and PDH frequencies as well as other fre-
quencies. The references are continually monitored for loss of signal
and for frequency offset per user programmed thresholds. The active
reference for each of the two Digital PLLs (DPLLs) is determined by
forced selection or by automatic selection based on user programmed
priorities and locking allowances and based on the reference monitors.
The two IDT82V3396 timing paths are defined by independent
DPLLs with embedded clock synthesizers. Both DPLLs support three
primary operating modes: Free-Run, Locked and Holdover. In Free-Run
mode the DPLLs generate clocks based on the master clock alone. In
Locked mode the DPLLs filter reference clock jitter with one of the fol-
lowing selectable bandwidths: 18 Hz, 35 Hz, 70 Hz or 560 Hz. In Locked
mode the long-term DPLL frequency accuracy is the same as the long
term frequency accuracy of the selected input reference. In Holdover
mode the DPLL uses frequency data acquired while in Locked mode to
generate accurate frequencies for short periods.
The IDT82V3396 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLLs in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLLs in Free-Run mode and in Holdover mode.
The clocks synthesized by the IDT82V3392 DPLLs can be passed
through one of the two independent jitter attenuating APLLs (for jitter
sensitive applications). Any of the DPLL or APLL clocks can be routed
through a mux to any of the six clock outputs via independent output
The IDT82V3392 accepts sync pulse inputs that are associated with
input references; the sync pulses can have frequencies of 1 Hz, 2 kHz or
8 kHz. The device aligns its output sync pulses with the selected input
sync pulse.
All IDT82V3392 read/write registers are accessed through a SPI/I2C
microprocessor interface.
2 February 4, 2013

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT82V3396Dual Synchronous Ethernet Line Card PLLIntegrated Device Technology
Integrated Device Technology

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