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ICS950402 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - AMD - K8 System Clock Chip - Integrated Circuit Systems

भाग संख्या ICS950402
समारोह AMD - K8 System Clock Chip
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS950402?> डेटा पत्रक पीडीएफ

ICS950402 pdf
ICS950402
Pin Descriptions
PIN #
PIN NAME
1 *FS0/REF0
2 VDDREF
3 X1
4 X2
5 GND
6 *(PCICLK7/HTTCLK0)ModeA
7 *PCICLK8/HTTCLK1/ModeB
8 PCICLK9/HTTCLK2
9 VDDPCI
10 GND
11 ~PCICLK10/HTTCLK3
12 PCICLK11
13 PCICLK0
14 PCICLK1
15 GND
16 VDDPCI
17 ****PCICLK2
18 ****PCICLK3
19 VDDPCI
20 GND
21 PCICLK4
22 PCICLK5
23 ~*PCICLK_F/ModeC
24 ~*(PCICLK6)PCI_STOP#
25 SCLK
26 SDATA
27 GND
PIN
TYPE
I/O
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
I/O
PWR
PWR
OUT
OUT
I/O
I/O
IN
I/O
PWR
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
PCI clock output / Hyper Transport output / Mode selection pin, this input is activated by the
ModeB selection pin.
PCI clock output / Hyper Transport output / Mode selection latch input pin.
PCI clock output / Hyper Transport output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output / Hyper Transport output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Real time system reset signal for watchdog timer timeout. This signal is active low and
selected by Mode latch input / 3.3V PCI clock clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low / PCI clock
output, this output is activated by the Mode selection pin
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
besides the PCICLK_F clocks at logic 0 level, when input low.
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Ground pin.
28 24_48MHz/Sel24_48#*~
I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
29 AVDD48
30 GND
31 48MHz/FS3**
32 VDD
33 GND
34 GND
35 VDDCPU
36 CPUCLK8C1
37 CPUCLK8T1
38 VDDCPU
39 GND
40 CPUCLK8C0
41 CPUCLK8T0
42 GND
43 VDDA
44 Reset#
45 REF2/FS2*
46 VDDREF
47 GND
PWR
PWR
I/O
PWR
PWR
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
I/O
PWR
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Ground pin.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Power supply, nominal 3.3V
Ground pin.
Ground pin.
Supply for CPU clocks, 3.3V nominal
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Ground pin.
"Complimentary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Ground pin.
3.3V power for the PLL core.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
14.318 MHz reference clock / Frequency select latch input pin.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
48 REF1/FS1*
I/O 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
**** This Output has 2.3X Drive Strength
0700B—04/30/04
Downloaded from Elcodis.com electronic components distributor
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