DataSheet.in

ICS95V847 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V Wide Range Frequency Clock Driver - Integrated Circuit Systems

भाग संख्या ICS95V847
समारोह 2.5V Wide Range Frequency Clock Driver
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS95V847?> डेटा पत्रक पीडीएफ

ICS95V847 pdf
ICS95V8 47
Pin Descriptions
PIN NUMBER
PIN NAME
5, 12, 20
VDD
1, 4, 13
GND
8 AVDD
9 AGND
3, 11, 15, 21, 24 CLKT[0:4]
2, 10, 14, 22, 23 CLKC[0:4]
6 CLK_INT
7 CLK_INC
16 FB_OUTT
17 FB_OUTC
19 FB_INT
18 FB_INC
TYPE
DESCRIPTION
PWR Power supply, 2.5V
PWR Ground
PWR
PWR
OUT
Analog power supply, 2.5V
Analog ground
"True" Clock of differential pair outputs
OUT "Complementary" clocks of differential pair outputs
IN "True" reference clock input
IN
OUT
OUT
IN
IN
"Complementary" reference clock input
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC).The
clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog
power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS95V847 is characterized for operation from 0°C to 85°C.
0718E—11/24/08
2

विन्यास 9 पेज
डाउनलोड[ ICS95V847 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS95V842DDR Phase Lock Loop Clock DriverIntegrated Circuit Systems
Integrated Circuit Systems
ICS95V8472.5V Wide Range Frequency Clock DriverIntegrated Circuit Systems
Integrated Circuit Systems


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English