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HIP1016 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Power Distribution Controllers - Intersil Corporation

भाग संख्या HIP1016
समारोह Power Distribution Controllers
मैन्युफैक्चरर्स Intersil Corporation 
लोगो Intersil Corporation लोगो 
पूर्व दर्शन
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<?=HIP1016?> डेटा पत्रक पीडीएफ

HIP1016 pdf
HIP1015, ISL6115, HIP1016, ISL6116
Simplified Block Diagram
ISET
ISEN
GATE
VSS
10µA
18V
UV
-
+
+
VREF
-
VDD
+
-
+ POR
8V
-
QN R
R
QS
ENABLE
12V
ISL611X
UV DISABLE
OC +
-
7.5k
CLIM
FALLING
EDGE
DELAY
ENABLE
-
+
WOCLIM
20µA
18V
20µA
+
-
1.86V
+
-
RISING
EDGE
PULSE
PWRON
PGOOD
CTIM
VDD
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
SYMBOL
ISET
ISEN
GATE
VSS
VDD
CTIM
PGOOD
PWRON
FUNCTION
DESCRIPTION
Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor. This
pin functions as the current limit programming pin.
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this resistor.
External FET Gate Drive
Pin
Chip Return
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (HIP1015,
ISL6115) and to VDD (HIP1016, ISL6116) by a 10µA current source.
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated VSS +12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay between
an overcurrent event and chip output shutdown (current limit time-out). The duration of current
limit time-out (in seconds) = 93kx CTIM (Farads).
Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output is not within specification. On the
ISL6115 and ISL6116, PGOOD function is enabled once IC is properly biased. On the
HIP1015 and HIP1016 the PGOOD function is disabled until the GATE voltage is within +/-
2.5V of VDD.
Power ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high or is open. After a current limit time out, the chip is reset by a low level signal applied to
this pin. This input has 20µA pull up capability.
2

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डाउनलोड[ HIP1016 Datasheet.PDF ]


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