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LC4256C-5F256BI डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Super Fast High Density PLDs - Lattice Semiconductor

भाग संख्या LC4256C-5F256BI
समारोह Super Fast High Density PLDs
मैन्युफैक्चरर्स Lattice Semiconductor 
लोगो Lattice Semiconductor लोगो 
पूर्व दर्शन
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LC4256C-5F256BI pdf
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Table 2. ispMACH 4000Z Family Selection Guide
Macrocells
I/O + Dedicated Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltage (V)
Max. Standby Icc (µA)
Pins/Package
ispMACH 4032ZC
32
32+4/32+4
3.5
2.2
3.0
267
1.8
20
48 TQFP
56 csBGA
ispMACH 4064ZC
64
32+4/32+12/
64+10/64+10
3.7
2.5
3.2
250
1.8
25
48 TQFP
56 csBGA
100 TQFP
132 csBGA
ispMACH 4128ZC
128
64+10/96+4
4.2
2.7
3.5
220
1.8
35
100 TQFP
132csBGA
ispMACH 4256ZC
256
64+10/96+6/
128+4
4.5
2.9
3.8
200
1.8
55
100 TQFP
132 csBGA
176 TQFP
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on signicant innovations to combine the highest performance with low
power in a exible CPLD family.
The ispMACH 4000 combines high speed and low power with the exibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch BGA (fpBGA) packages ranging
from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is congured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment.
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
2

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भाग संख्याविवरणविनिर्माण
LC4256C-5F256BCSuper Fast High Density PLDsLattice Semiconductor
Lattice Semiconductor
LC4256C-5F256BISuper Fast High Density PLDsLattice Semiconductor
Lattice Semiconductor


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