Integrated

Circuit

Systems, Inc.

ICS9LPRS480

MLF Pin Description

PIN #

PIN NAME

1 GND48

2 SMBCLK

3 SMBDAT

4 VDD27

PIN TYPE

GND

IN

I/O

PWR

DESCRIPTION

Ground pin for the 48MHz outputs

Clock pin of SMBus circuitry, 5V tolerant.

Data pin for SMBus circuitry, 5V tolerant.

3.3V Power supply for SRC/27MHz output and 27MHz SS PLL

5 SRC7C_LPRS/27MHz_NS

OUT

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)/27MHz 3.3V Single-ended non-spread output for discrete graphics

6 SRC7T_LPRS/27MHz_SS

7 GND27

8 SRC4C_LPRS

9 SRC4T_LPRS

10 GNDSRC

11 VDDSRC_IO

12 SRC3C_LPRS

13 SRC3T_LPRS

14 SRC2C_LPRS

15 SRC2T_LPRS

16 VDDSRC

17 VDDSRC_IO

18 GNDSRC

19 SRC1C_LPRS

20 SRC1T_LPRS

21 SRC0C_LPRS

22 SRC0T_LPRS

23 *CLKREQ0#

24 GNDATIG

25 VDDATIG_IO

26 VDDATIG

27 ATIG1C_LPRS

28 ATIG1T_LPRS

29 ATIG0C_LPRS

30 ATIG0T_LPRS

31 SB_SRC1C_LPRS

32 SB_SRC1T_LPRS

OUT

GND

OUT

OUT

GND

PWR

OUT

OUT

OUT

OUT

PWR

PWR

GND

OUT

OUT

OUT

OUT

IN

GND

PWR

PWR

OUT

OUT

OUT

OUT

OUT

OUT

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended spreading output for discrete

graphics

Ground for the SRC/27MHz outputs

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

Ground pin for the SRC outputs

Power supply for differential SRC outputs, nominal 1.05V to 3.3V

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

Supply for SRC core, 3.3V nominal

Power supply for differential SRC outputs, nominal 1.05V to 3.3V

Ground pin for the SRC outputs

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND

and no 33 ohm series resistor needed)

True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33

ohm series resistor needed)

Clock Request pin for SRC0 outputs. If output is selected for control, then that output is controlled

as follows:

0 = enabled, 1 = Low-Low

Ground pin for the ATIG outputs

Power supply for differential ATIG outputs, nominal 1.05V to 3.3V

Power supply for ATIG core, nominal 3.3V

Complementary clock of low-power differential push-pull PCI-Express pair with integrated series

resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)

True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no

50ohm shunt resistor to GND and no 33 ohm series resistor needed)

Complementary clock of low-power differential push-pull PCI-Express pair with integrated series

resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)

True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no

50ohm shunt resistor to GND and no 33 ohm series resistor needed)

Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt

resistor to GND and no 33 ohm series resistor needed

True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor

to GND and no 33 ohm series resistor needed

1391D—02/02/09

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