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ICS9LPRS462 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Power Clock - Integrated Device Technology

भाग संख्या ICS9LPRS462
समारोह Low Power Clock
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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<?=ICS9LPRS462?> डेटा पत्रक पीडीएफ

ICS9LPRS462 pdf
ICS9LPRS462
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
Pin Description
PIN #
1 GNDREF
2 VDDREF
3 X1
4 X2
5 VDD48
6 48MHz_0
7 48MHz_1
8 GND48
9 SMBCLK
10 SMBDAT
PIN NAME
11 RESET_IN#
12 SRC7T_LPR
13 SRC7C_LPR
14 VDDSRC
15 GNDSRC
16 SRC6T_LPR
17 SRC6C_LPR
18 SRC5T_LPR
19 SRC5C_LPR
20 SRC4T_LPR
21 SRC4C_LPR
22 GNDSRC
23 VDDSRC
24 SRC3T_LPR
25 SRC3C_LPR
26 SRC2T_LPR
27 SRC2C_LPR
28 VDDSRC
29 GNDSRC
30 ATIG3T_LPR
31 ATIG3C_LPR
32 *CLKREQB#
TYPE
GND
PWR
IN
OUT
PWR
OUT
OUT
GND
IN
I/O
IN
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
IN
DESCRIPTION
Ground pin for the REF outputs.
Ref, XTAL power supply, nominal 3.3V
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
48MHz clock output.
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Real Time falling edge triggered input, When asserted, the part initiates a power up
reset with the SMBus being reset to it's power up values, and all PLL derived clocks
stopped for the duration of Power up Stabilization. REF outputs continue to run.
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
Supply for SRC, 3.3V nominal
Ground pin for the SRC outputs
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
Ground pin for the SRC outputs
Supply for SRC, 3.3V nominal
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
Supply for SRC, 3.3V nominal
Ground pin for the SRC outputs
True clock of low-power differential push-pull PCI-Express pair with integrated 33 ohm
series resistor. (no 50ohm shunt resistor to GND needed)
Complementary clock of low-power differential push-pull PCI-Express pair with
integrated 33 ohm series resistor. (no 50ohm shunt resistor to GND needed)
Programmable Clock Request pin for SRC/ATIG/SB_SRC outputs. If output is selected
for control, then that output is controlled as follows:
0 = Enabled, 1 = Tri-state
IDTTM/ICSTM Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
2
1378A—04/07/08

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