DataSheet.in

ICS9UMS9633B डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - ULTRA MOBILE PC/MOBILE INTERNET DEVICE - IDT

भाग संख्या ICS9UMS9633B
समारोह ULTRA MOBILE PC/MOBILE INTERNET DEVICE
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS9UMS9633B?> डेटा पत्रक पीडीएफ

ICS9UMS9633B pdf
www.DataSheet.co.kr
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
SSOP Pin Description
PIN #
PIN NAME
1 REF
2 GNDREF
3 VDDCORE_3.3
4 FSC_L
5 TEST_MODE
6 TEST_SEL
7 SCLK
8 SDATA
9 VDDCORE_3.3
10 VDDIO_1.5
11 DOT96C_LPR
12 DOT96T_LPR
13 GNDDOT
14 GNDLCD
15 LCD100C_LPR
16 LCD100T_LPR
17 VDDIO_1.5
18 VDDCORE_3.3
19 *CR#0
20 GNDSRC
21 SRCC0_LPR
22 SRCT0_LPR
23 *CR#1
24 VDDCORE_3.3
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
IN 1 = All outputs are tri-stated for test
0 = All outputs behave normally.
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
OUT Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN Clock request for SRC0, 0 = enable, 1 = disable
PWR Ground pin for the SRC outputs
OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
2
1423—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/

विन्यास 22 पेज
डाउनलोड[ ICS9UMS9633B Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS9UMS9633BULTRA MOBILE PC/MOBILE INTERNET DEVICEIDT
IDT
ICS9UMS9633BIULTRA MOBILE PC CLOCKIDT
IDT


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English