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IS42VS16400C1 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM - Integrated Silicon Solution

भाग संख्या IS42VS16400C1
समारोह 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
मैन्युफैक्चरर्स Integrated Silicon Solution 
लोगो Integrated Silicon Solution लोगो 
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IS42VS16400C1 pdf
IS42VS16400C1
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 1.8V memory
systems containing 67,108,864 bits. Internally configured
as a quad-bank DRAM with a synchronous interface. Each
16,777,216-bit bank is organized as 4,096 rows by 256
columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
ISSI ®
www.DataSheet4U.com
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
12
ROW
ADDRESS
12 LATCH
COLUMN
ADDRESS LATCH
8
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
12
DATA IN
BUFFER
16 16
DQM
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
GND/GNDQ
4096
4096
4096
MEMORY CELL
12
4096
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
256K
(x 16)
COLUMN DECODER
8
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05

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डाउनलोड[ IS42VS16400C1 Datasheet.PDF ]


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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IS42VS16400C11 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAMIntegrated Silicon Solution
Integrated Silicon Solution


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