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IDT88P8344 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 - Integrated Device Technology

भाग संख्या IDT88P8344
समारोह SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT88P8344 pdf
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
Table of Contents
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Features ........................................................................................................................................................................................................................ 1
Applications .................................................................................................................................................................................................................. 1
1. Introduction ............................................................................................................................................................................................................. 8
2. Pin description ......................................................................................................................................................................................................... 9
3. External interfaces ................................................................................................................................................................................................. 13
3.1 SPI-3 ............................................................................................................................................................................................................... 13
3.1.1 SPI-3 ingress ........................................................................................................................................................................................ 13
3.1.2 SPI-3 egress ........................................................................................................................................................................................ 15
3.2 SPI-4 ............................................................................................................................................................................................................... 17
3.2.1 SPI-4 ingress ........................................................................................................................................................................................ 17
3.2.2 SPI-4 egress ........................................................................................................................................................................................ 20
3.2.3 SPI-4 startup handshake ....................................................................................................................................................................... 20
3.3 Microprocessor interface .................................................................................................................................................................................. 22
4. Datapath and flow control .................................................................................................................................................................................... 23
4.1 SPI-3 to SPI-4 datapath and flow control .......................................................................................................................................................... 25
4.2 SPI-4 to SPI-3 datapath and flow control .......................................................................................................................................................... 30
4.3 SPI-3 ingress to SPI-3 egress datapath ............................................................................................................................................................ 33
4.4 Microprocessor interface to SPI-3 datapath ...................................................................................................................................................... 34
4.4.1 SPI-3 to ingress microprocessor interface datapath ................................................................................................................................ 34
4.4.2 Microprocessor insert to SPI-3 egress datapath ..................................................................................................................................... 35
4.4.3 Microprocessor interface to SPI-4 egress datapath ................................................................................................................................ 36
4.4.4 SPI-4 ingress to microprocessor interface datapath ................................................................................................................................ 37
5. Performance monitor and diagnostics ................................................................................................................................................................. 38
5.1 Mode of operation ............................................................................................................................................................................................ 38
5.2 Counters ......................................................................................................................................................................................................... 38
5.2.1 LID associated event counters ............................................................................................................................................................... 38
5.2.2 Non - LID associated event counters ..................................................................................................................................................... 38
5.3 Captured events .............................................................................................................................................................................................. 38
5.3.1 Non LID associated events .................................................................................................................................................................... 38
5.3.2 LID associated events ........................................................................................................................................................................... 38
5.3.2.1 Non critical events ...................................................................................................................................................................... 38
5.3.2.2 Critical events ............................................................................................................................................................................. 38
5.3.3 Timebase .............................................................................................................................................................................................. 38
5.3.3.1 Internally generated timebase ..................................................................................................................................................... 38
5.3.3.2 Externally generated timebase .................................................................................................................................................... 38
6. Clock generator ...................................................................................................................................................................................................... 39
7. Loopbacks .............................................................................................................................................................................................................. 40
7.1 SPI-3 Loopback ............................................................................................................................................................................................... 40
8. Operation guide ..................................................................................................................................................................................................... 41
8.1 Hardware operation ........................................................................................................................................................................................ 41
8.1.1 System reset ......................................................................................................................................................................................... 41
8.1.2 Power on sequence .............................................................................................................................................................................. 41
8.1.3 Clock domains ...................................................................................................................................................................................... 41
8.2 Software operation ........................................................................................................................................................................................... 41
8.2.1 Chip configuration sequence ................................................................................................................................................................. 41
8.2.2 Logical Port activation and deactivation .................................................................................................................................................. 42
8.2.3 Buffer segment modification .................................................................................................................................................................... 42
8.2.4 Manual SPI-4 ingress LVDS bit alignment .............................................................................................................................................. 42
8.2.5 SPI-4 status channel software ............................................................................................................................................................... 43
8.2.6 IDT88P8344 layout guidelines .............................................................................................................................................................. 43
8.2.7 Software Eye-Opening Check on SPI-4 Interface .................................................................................................................................. 44
9. Register description .............................................................................................................................................................................................. 46
9.1 Register access summary ................................................................................................................................................................................ 46
9.1.1 Direct register format ............................................................................................................................................................................. 46
9.1.2 Indirect register format ........................................................................................................................................................................... 46
9.2 Direct access registers ..................................................................................................................................................................................... 50
2 APRIL 10, 2006

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