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A1174 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Ultrasensitive Hall Effect Latch - Allegro MicroSystems

भाग संख्या A1174
समारोह Ultrasensitive Hall Effect Latch
मैन्युफैक्चरर्स Allegro MicroSystems 
लोगो Allegro MicroSystems लोगो 
पूर्व दर्शन
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<?=A1174?> डेटा पत्रक पीडीएफ

A1174 pdf
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
Description (continued)
wwawch.diaevtaeshseyent4chu.rcoonmous clocking of multiple devices. This allows a
defined phase relationship between the output transitions of each
device in direction detection systems.
Improved stability is made possible through dynamic offset
cancellation using chopper stabilization, which reduces the residual
offset voltage normally caused by device overmolding, temperature
dependencies, and thermal stress. Solid state reliability is provided
by integrating, on a single silicon chip, a Hall-voltage generator,
a small-signal amplifier, chopper stabilization, a latch, and a
MOSFET output.
The device package is a 6-contact, 1.5 mm × 2 mm, 0.40 mm nominal
overall height MLP/DFN, with exposed pad for enhanced thermal
dissipation. It is lead (Pb) free, with 100% matte tin leadframe
plating.
Selection Guide
Part Number
Packing*
A1174EEWLT-T
3000 pieces per 7-inch reel
*Contact Allegro® for additional packing options
Absolute Maximum Ratings
Characteristic
Forward Supply Voltage
Reverse Supply Voltage
Output Voltage
Reverse Output Voltage
EXTERNAL_CLK and DUAL_CLK
Pins Input Voltage
EXTERNAL_CLK and DUAL_CLK
Pins Reverse Input Voltage
Continuous Output Current
Magnetic Flux Density*
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
*1G = 0.1 mT (millitesla)
Symbol
VDD
VRDD
VOUT
VROUT
VIN
VRIN
IOUT(sink)
IOUT(source)
B
TA
TJ(MAX)
Tstg
Range E
Notes
Rating
5.0
–0.3
5.0
–0.3
5.0
–0.3
–1
1
Unlimited
–40 to 85
165
–65 to 170
Units
V
V
V
V
V
V
mA
mA
G
°C
°C
°C
Pin-out Diagram
VDD 1
6 DUAL_CLK
NC 2 PAD 5 GND
VOUT 3
4 EXTERNAL_CLK
(Top View)
Terminal List
Number
1
Name
VDD
2 NC
Supply Voltage
No connect
Function
3
VOUT
Output
4
EXTERNAL_CLK
In combination with DUAL_CLK , allows external control of the device
sampling period and duty cycle
5
GND
Ground
6
DUAL_CLK
In combination with EXTERNAL_CLK , drives the part in Dual Clock mode
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2

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