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IDT82V3155 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - ENHANCED T1/E1/OC3 WAN PLL - Integrated Device Technology

भाग संख्या IDT82V3155
समारोह ENHANCED T1/E1/OC3 WAN PLL
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT82V3155 pdf
IDT82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE
DESCRIPTION
The IDT82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual
referewncwewi.nDpauttasS. hIteceotn4tUa.icnosma Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and
framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048
MHz or 19.44 MHz input reference.
The IDT82V3155 provides 10 types of clock signals (C1.5o, C3o,
C6o, C2o, C4o, C8o, C16o, C19o, C32o, C155) and 7 types of framing
signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1
and STS3/OC3 links.
The IDT82V3155 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port,
155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1,
and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance,
jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture
range, phase change slope, holdover frequency accuracy and MTIE
(Maximum Time Interval Error) requirements for these specifications.
The IDT82V3155 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
source. It also can be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
MODE_sel0
MODE_sel1
TCLR
RST
Fref0
Fref1
MON_out0
MON_out1
F0_sel0
F0_sel1
IN_sel
VSS
VDD
C6o
C1.5o
C3o
C2o
VSS
VDD
C4o
C155POS
C155NEG
C8o
C16o
C32o
VDD
VSS
TCK
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 IDT82V3155 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
TIE_en
IC2
C2/C1.5
IC0
HOLDOVER
FREERUN
OSCi
F19o
VDD
VSS
NORMAL
FLOCK
LOCK
C19o
TSP
RSP
F32o
F16o
VSS
VDD
F8o
F1_sel0
F1_sel1
F0o
TDI
TMS
TRST
TDO
Figure - 1 IDT82V3155 SSOP56 Package Pin Assignment
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT82V3155ENHANCED T1/E1/OC3 WAN PLLIntegrated Device Technology
Integrated Device Technology


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