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ICS9LPR426A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Power Programmable Timing Control Hub - Integrated Circuit Systems

भाग संख्या ICS9LPR426A
समारोह Low Power Programmable Timing Control Hub
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS9LPR426A?> डेटा पत्रक पीडीएफ

ICS9LPR426A pdf
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Pin Description
PIN #
1
2
PIN NAME
VDDPCI
GND
3 PCICLK3
4 PCICLK4
5 *SELPCIEX0_LCD#PCICLK5
6 GND
7 VDDPCI
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8 ITP_EN/PCICLK_F0
9 *SELLCD_27#/PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 FSLA/USB_48MHz
13 GND
14 DOTT_96MHzL
15 DOTC_96MHzL
16 FSLB/TEST_MODE
17 27FIX/LCD_SSCGT/PCIeT_L0
18 27SS/LCD_SSCGC/PCIeC_L0
19 PCIeT_L1
20 PCIeC_L1
21 VDDPCIEX
22 PCIeT_L2
23 PCIeC_L2
24 PCIeT_L3
25 PCIeC_L3
26 SATACLKT_L
27 SATACLKC_L
28 VDDPCIEX
TYPE
PWR
PWR
OUT
OUT
I/O
PWR
PWR
I/O
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock
output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP#.
SELLCD_27#: latched input to select pin functionality
1 = LCDCLK pair
0 = 27MHzSS/27MHzSS# pair
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be
sampled. PD is an asynchronous active high input pin used to put the device into a low
power state. The internal clocks, PLLs and the crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
Ground pin.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm to GND
needed.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed.
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True
clock of low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output /
Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND
needed)
Power supply for PCI Express clocks, nominal 3.3V
1346—10/23/07
2

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अनुशंसा डेटापत्रक

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