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ICS952906A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Control Hub - ICS

भाग संख्या ICS952906A
समारोह Programmable Timing Control Hub
मैन्युफैक्चरर्स ICS 
लोगो ICS लोगो 
पूर्व दर्शन
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<?=ICS952906A?> डेटा पत्रक पीडीएफ

ICS952906A pdf
Integrated
Circuit
Systems, Inc.
ICS952906A
Pin Description
PIN # PIN NAME
1 *FS1/REF0
2 **FS0/REF1
3 VDDREF
4 X1
5 X2
6 GND
7 **FS2/PCICLK_F0
8 **FS4/PCICLK_F1
9 PCICLK_F2
10 VDDPCI
www.DataShee1t41U.coGmND
12 **MODE/PCICLK0
13 PCICLK1
14 PCICLK2
15 PCICLK3
16 PCICLK4
17 VDDPCI
18 GND
19 PCICLK5
20 PCICLK6
21 **FS3/48MHz
PIN TYPE
I/O
I/O
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
I/O
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP
inputs) / PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
22 **Sel24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz.
23 GND
24 VDD48
25 3V66_2
26 3V66_1
27 VDD3V66
28 GND
29 3V66_0
30 Reset#
31 SCLK
32 SDATA
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
Ground pin.
Power pin for the 48MHz output.3.3V
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is
active low.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
33 VttPWR_GD/PD#
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready
IN to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the
device into a low power state.
34 VDD2.5
35 25Mhz_1
36 25Mhz_0
37 GND
38 CPUCLKC0
39 CPUCLKT0
40 VDDCPU
41 CPUCLKC1
42 CPUCLKT1
43 GND
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
Power supply, nominal 2.5V
25MHz clock output, 2.5V
25MHz clock output, 2.5V
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Ground pin.
44 CPUCLKC_ITP/(CPU_STOP#) I/O
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias. / Stops all CPUCLK besides the free running clocks
45 CPUCLKT_ITP/(PCI_STOP#) I/O
46 IREF
47 GND
48 VDDA
OUT
PWR
PWR
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias. / Stops all PCICLK besides the free running clocks
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
value.
Ground pin.
3.3V power for the PLL core.
1236A—08/06/07
2

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