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LM2326 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - PLLatinum Low Power Frequency Synthesizer for RF Personal Communications - National Semiconductor

भाग संख्या LM2326
समारोह PLLatinum Low Power Frequency Synthesizer for RF Personal Communications
मैन्युफैक्चरर्स National Semiconductor 
लोगो National Semiconductor लोगो 
पूर्व दर्शन
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<?=LM2326?> डेटा पत्रक पीडीएफ

LM2326 pdf
Connection Diagrams
LMX2306/16/26
LMX2306/16/26
DS100127-2
16-Lead (0.173” Wide) Thin Shrink Small Outline
Package(TM)
Order Number LMX2306TM, LMX2306TMX,
LMX2316TM, LMX2316TMX,
LMX2326TM or LMX2326TMX
See NS Package Number MTC16
Pin Descriptions
DS100127-19
16-pin Chip Scale Package
Order Number LMX2306SLBX, LMX2316SLBX or
LM2326SLBX
See NS Package Number SLB16A
16-Pin 16-Pin
TSSOP CSP
1 15
2 16
31
42
53
64
75
86
97
10 8
11 9
12 10
13 11
14 12
15 13
16 14
Pin I/O
Name
FLo O
CPo
GND
GND
fIN
O
I
fIN
VCC1
I
OSCIN I
GND
CE
I
Clock I
Data I
LE I
Fo/LD O
VCC2
VP
Description
FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4
FASTLOCK MODES description.)
Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
Charge Pump Ground.
Analog Ground.
RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.
RF Prescaler Input. Small signal input from the VCO.
Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. VCC1
must equal VCC2.
Oscillator Input. This input is a CMOS input with a threshold of approximately VCC/2 and an
equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.
Digital Ground.
Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.
Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING VCC.)
High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge
into the 21-bit shift register.
Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one
of the 3 appropriate latches (control bit dependent).
Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.
(See Table 4.)
Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. VCC1
must equal VCC2.
Power Supply for Charge Pump. Must be VCC.
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