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ICS951901 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Frequency Generator & Integrated Buffers - ICS

भाग संख्या ICS951901
समारोह Programmable Frequency Generator & Integrated Buffers
मैन्युफैक्चरर्स ICS 
लोगो ICS लोगो 
पूर्व दर्शन
1 Page
		
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ICS951901 pdf
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ICS951901
General Description
The ICS951901 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
The ICS951901 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
MODE Pin Power Management Control Input
MODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
0 SDRAM11 SDRAM10
SDRAM9
SDRAM8
1 CPU_STOP# PCI_STOP# SDRAM_STOP# PD#
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16,
20
PIN NAME
VDD
AGPSEL
REF0
FS3
REF1
GND
X1
X2
FS1
PCICLK_F
FS2
PCICLK0
PCICLK (4:1)
AGP (1:0)
FS0
48MHz
21 MODE
24_48MHz
23 SDATA
24 SCLK
27 CPU_STOP#
SDRAM11
28 PCI_STOP#
SDRAM10
SDRAM9
30
SDRAM_STOP#
31 PD#
26 33, 34, 36,
37, 38, 40, 41,
42
45, 46, 47
48
0670B—07/15/04
SDRAM8
SDRAM (12,
7:0)
CPUCLK (2:0)
VDDL
TYPE
PWR
IN
OUT
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
PWR
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48MHz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
Clock output for super I/O/USB default is 24MHz
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode
SDRAM clock output
Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
SDRAM clock output
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms
SDRAM clock output
SDRAM clock outputs
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2

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