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IDT71V25781 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - (IDT71V25761 / IDT71V25781) Synchronous SRAMs - IDT

भाग संख्या IDT71V25781
समारोह (IDT71V25761 / IDT71V25781) Synchronous SRAMs
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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IDT71V25781 pdf
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
A0-A17
ADSC
ADSP
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
I
I
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the
Advance
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
CE
Chip Enable
I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V25761/781.
CE also gates ADSP.
CLK
Clock
I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS0
Chip Select 0
I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
Enable
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE
Output Enable
I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 2.5V I/O Supply.
VSS
Ground
N/A N/A Ground.
NC
No Connect
N/A N/A NC pins are not electrically connected to the device.
ZZ
Sleep Mode
I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V25761/781 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5297 tbl 02
6.422

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डाउनलोड[ IDT71V25781 Datasheet.PDF ]


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