DataSheet.in

IDT71V433 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Synchronous SRAM - IDT

भाग संख्या IDT71V433
समारोह Synchronous SRAM
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT71V433?> डेटा पत्रक पीडीएफ

IDT71V433 pdf
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Pin Definitions(1)
Commercial and Industrial Temperature Ranges
Symbol
Pin Function
I/O Active Description
A0–A14
ADSC
ADSP
Address Inputs
Address Status
(Cache Controller)
Address Status (Processor)
I
I
I
N/A Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input
that is used to load the address registers with new addresses. ADSC is NOT gated
by CE.
LOW Synchronous Address Status from Processor. ADSP is an active LOW input that
is used to load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address Advance
I
BWE
Byte Write Enable
I
BW1BW4
CE
Individual Byte Write
Enables
Chip Enable
I
I
LOW Sync hrono us Ad dress Adv ance. ADV is an ac tive LOW input that is used to
advance the internal burst counter, controlling burst access after the initial address
is loaded. When this input is HIGH the burst counter is not incremented; that is,
there is no address advance.
LOW Synchronous b yte write enable gates the byte write inputs BW1BW4. If BWE is
LOW at the rising edge of CLK then BWX inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
LOW Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW disables
all byte writes. BW1BW4 must meet specified setup and hold times with respect
to CLK.
LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V433.
CE also gates ADSP.
CLK
Clock
I N/A This is the clock input. All timing references for the device are made with respect
to this input.
CS0
Chip Select 0
I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the
chip.
CS1
Chip Select 1
I LOW Synchro nous active LOW chip select. CS1 is used with CE and CS0 to enable the
chip.
GW
Global Write Enable
I LOW Synchronous global write enable. This input will write all four 8-bit data bytes when
LOW on the rising edge of CLK. GW supercedes individual byte write enables.
I/O0–I/O31
LBO
OE
Data Input/Output
Linear Burst
Output Enable
I/O N/A Synchronous data input/output (I/O) pins. Only the data input path is registered
and triggered by the rising edge of CLK. Outputs are Flow-Through.
I LOW When LBO is HIGH the Interleaved Order (Intel) burst sequence is selected. When
LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO has an internal
pull-up resistor.
I LOW Asynchronous output e nable. Whe n OE is HIGH the I/O pins are in a high-
impedence state. When OE is LOW the data output drivers are enabled if the chip
is also selected.
VDD
Power Supply
N/A N/A 3.3V core power supply inputs.
VDDQ
Power Supply
N/A N/A 3.3V I/O power supply inputs.
VSS
Ground
N/A N/A Core ground pins.
VSSQ
Ground
N/A N/A I/O ground pins.
NC
No Connect
N/A N/A NC pins are not electrically connected to the chip.
ZZ
Sleep Mode
I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V433 to its lowe st power consumption level. Data retention is
guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3729 tbl 02
2

विन्यास 19 पेज
डाउनलोड[ IDT71V433 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT71V43232K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle DeselectIntegrated Device Technology
Integrated Device Technology
IDT71V433Synchronous SRAMIDT
IDT


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English