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IDT71V2577S डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - (IDT71V2577S / IDT71V25779) Synchronous SRAMs - IDT

भाग संख्या IDT71V2577S
समारोह (IDT71V2577S / IDT71V25779) Synchronous SRAMs
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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IDT71V2577S pdf
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definition(1)
Symbol
Pin Function
I/O Active
Description
A0-A17
ADSC
ADSP
ADV
BWE
Address Inputs
Address Status
(Cache Controller)
Address Status
(Processor)
Burst Address
Advance
Byte Write Enable
I
I
I
I
I
BW1-BW4
CE
Individual Byte
Write Enables
Chip Enable
I
I
N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of
CLK and ADSC Low or ADSP Low and CE Low.
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst
counter is not incremented; that is, there is no address advance.
LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of
CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs
are blocked and only GW can initiate a write cycle.
LOW Synchro nous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active
byte write causes all outputs to be disabled.
LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V2577/79. CE also gates
ADSP.
CLK
Clock
I N/A This is the clock input. All timing references for the device are made with respect to this input.
CS0
Chip Select 0
I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
Enable
edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
LBO
Data Input/Output
Linear Burst Order
I/O
I
OE
Output Enable
I
N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge
of CLK. The data output path is flow-through (no output register).
LOW Asynchronous burst ord er selection input. When LBO is HIGH, the inter-leaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not
change state while the device is operating.
LOW Asynchrono us output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the
chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS
Test ModeSelect
I
N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test DataOutput
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional)
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
I LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST
can be left floating. This pin has an internal pullup. Only available in BGA package.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK inte rnally and power down the IDT71V2577/79
ZZ
Sleep Mode
I HIGH to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.
VDD
Power Supply
N/A N/A 3.3V core power supply.
VDDQ
Power Supply
N/A N/A 2.5V I/O Supply.
VSS
Ground
N/A N/A Ground.
NC
No Connect
N/A N/A NC pins are not electrically connected to the device.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
4877 tbl 02
6.422

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डाउनलोड[ IDT71V2577S Datasheet.PDF ]


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