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HLX6228 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 128K x 8 STATIC RAM-Low Power SOI - Honeywell

भाग संख्या HLX6228
समारोह 128K x 8 STATIC RAM-Low Power SOI
मैन्युफैक्चरर्स Honeywell 
लोगो Honeywell लोगो 
पूर्व दर्शन
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HLX6228 pdf
HLX6228
FUNCTIONAL DIAGRAM
A:3-7,12,14-16
CE
NCS
NWE
NOE
9
A:0-2, 8-11, 13
8
Row
Decoder
131,072 x 8
Memory
Array
•••
Column Decoder
Data Input/Output
WE • CS • CE
8
8
DQ:0-7
NWE • CS • CE • OE
(0 = high Z)
1 = enabled
Signal
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-16 Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it
requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse
to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.
The part must be controlled in this fashion to meet the timing specifications defined.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE NWE NOE
MODE
DQ
L H H L Read Data Out
L
H
LX
Write
Data In
Notes:
X: VI=VIH or VIL
H X XX XX Deselected High Z
XX: VSSVIVDD
X L XX XX Disabled High Z NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
HLX6228128K x 8 STATIC RAM-Low Power SOIHoneywell
Honeywell


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