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IDT728981 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 - IDT

भाग संख्या IDT728981
समारोह TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=IDT728981?> डेटा पत्रक पीडीएफ

IDT728981 pdf
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
PIN CON.IGURATION
INDEX
INDEX
RX3
VCC
VCC
VCC
VCC
VCC
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39 TX3
38 DNC(1)
37 DNC(1)
36 DNC(1)
35 DNC(1)
34 GND
33 D0
32 D1
31 D2
30 D3
29 D4
5703 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
NOTE:
1. DNC - Do Not Connect
PIN DESCRIPTIONS
SYMBOL
NAME
I/O
RX3
VCC
VCC
VCC
VCC
VCC
F0i
C4i
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
33 TX3
32 DNC(1)
31 DNC(1)
30 DNC(1)
29 DNC(1)
28 GND
27 D0
26 D1
25 D2
24 D3
23 D4
DTA
RX0
RX1
RX2
RX3
VCC
VCC
VCC
VCC
VCC
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 DNC(1)
39 ODE
38 TX0
37 TX1
36 TX2
35 TX3
34 DNC(1)
33 DNC(1)
32 DNC(1)
31 DNC(1)
30 GND
29 D0
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 CS
5703 drw03
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
5703 drw04
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
DESCRIPTION
GND
VCC
DTA
RX0-3
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-3
ODE
Ground.
VCC
Data Acknowledgment
(Open Drain)
RX Input 0 to 3
Frame Pulse
Clock
Address 0 to 5
Data Strobe
Read/Write
Chip Select
Data Bus 0 to 7
TX Outputs 0 to 3
(Three-state Outputs)
Output Drive Enable
Ground Rail.
+5.0 Volt Power Supply.
O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
I This input identifies frame synchronization signals formatted to ST-BUS® specifications.
I 4.096 MHz serial clock for shifting data in and out of the data streams.
I These lines provide the address to IDT728981 internal registers.
I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
I Active LOW input enabling a microprocessor read or write of control register or internal memories.
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
I This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
2

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डाउनलोड[ IDT728981 Datasheet.PDF ]


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