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IDT728980 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 - IDT

भाग संख्या IDT728980
समारोह TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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IDT728980 pdf
IDT728980 Time Slot Interchange
Digital Switch 256 x 256
PIN CON.IGURATION
Commercial Temperature Range
INDEX
INDEX
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39 TX3
38 TX4
37 TX5
36 TX6
35 TX7
34 GND
33 D0
32 D1
31 D2
30 D3
29 D4
5706 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
NOTE:
1. DNC - Do Not Connect.
PIN DESCRIPTIONS
SYMBOL
NAME
I/O
DTA
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
5706 drw04
CCO
ODE
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
GND
D0
D1
D2
D3
D4
D5
D6
D7
CS
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
33 TX3
32 TX4
31 TX5
30 TX6
29 TX7
28 GND
27 D0
26 D1
25 D2
24 D3
23 D4
5706 drw03
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
DESCRIPTION
GND
VCC
DTA
RX0-7
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-7
ODE
CCO
Ground.
Ground Rail.
VCC +5.0 Volt Power Supply.
Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
(Open Drain)
output.
RX Input 0 to 7
I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
Frame Pulse
I This input identifies frame synchronization signals formatted to ST-BUS® specifications.
Clock
I 4.096 MHz serial clock for shifting data in and out of the data streams.
Address 0 to 5
I These lines provide the address to IDT728980 internal registers.
Data Strobe
I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
Read/Write
I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Chip Select
I Active LOW input enabling a microprocessor read or write of control register or internal memories.
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX Outputs 0 to 7
(Three-state Outputs)
O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
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IDT
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