IDT72T51236 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - (IDT72T512x6) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES - Integrated Device Technology

भाग संख्या IDT72T51236
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
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IDT72T51236 pdf
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
The IDT72T51236/72T51246/72T51256 multi-queue flow-control de-
vices are single chip within which anywhere between 1 and 4 discrete FIFO
queues can be setup. All queues within the device have a common data input
bus, (write port) and a common data output bus, (read port). Data written into
the write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read from the read port is accessed
from a respective queue via an internal multiplex operation, addressed by the
user. Data writes and reads can be performed at high speeds up to 200MHz,
with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 4 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet mode of operation is also provided when the device is configured
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within
a queue is available for reading. The Packet Ready provides the user with
a means by which to mark the start and end of packets of data being passed
through the queues. The multi-queue device then provides the user with
an internally generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 4, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect toERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
The multi-queue flow-control has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSEL input. The core supply voltage (VCC) to the multi-queue is always 2.5V,
however the output levels can be set independently via a separate supply, VDDQ.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
of the functional blocks within the device.

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भाग संख्याविवरणविनिर्माण
IDT72T51236(IDT72T512x6) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICESIntegrated Device Technology
Integrated Device Technology

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