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IDT74LVC16601A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER - Integrated Device Technology

भाग संख्या IDT74LVC16601A
समारोह 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT74LVC16601A pdf
IDT74LVC16601A
3.3VCMOS18-BIT UNIVERSAL BUS TRANSCEIVER
PIN CONFIGURATION
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
SSOP/ TSSOP
TOP VIEW
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6 pF
COUT
Output Capacitance VOUT = 0V 6.5
8
pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
NOTE:
1. As applicable to the device type.
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
IOK VI < 0 or VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x A-to-B Data Inputs or B-to-A 3-State Outputs
B x B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB
A-to-B Clock Enable Input (Active LOW)
CLKENBA
B-to-A Clock Enable Input (Active LOW)
FUNCTION TABLE(1,2)
Inputs
Outputs
CLKENAB
X
X
X
H
L
L
L
OEAB
H
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
X
L
Ax
X
L
H
X
L
H
X
Bx
Z
L
H
B(3)
L
H
B(3)
L L L H X B(4)
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
= LOW-to-HIGH transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA,
and CLKENBA.
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
2

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IDT74LVC16601A3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERIntegrated Device Technology
Integrated Device Technology


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