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डेटा पत्रक - Two 0.7V current mode differential HCSL output pairs - Integrated Circuit Systems

भाग संख्या ICS9DB202
समारोह Two 0.7V current mode differential HCSL output pairs
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS9DB202?> डेटा पत्रक पीडीएफ

ICS9DB202 pdf
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 PLL_BW Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
2 CLK Input Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
4 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
5, 9, 12, 16
6, 15
7, 8
10, 11
13, 14
VDD
GND
PCIEXT0,
PCIEXC0
nOE0, nOE1
PCIEXC1,
PCIEXT1
Power
Power
Output
Input
Output
Core supply pins.
Power supply ground.
Differential output pairs. HCSL interface levels.
Pulldown
Output enable. When HIGH, forces outputs to HiZ state.
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
Differential output pairs. HCSL interface levels.
17 FS1 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
18
IREF
Input
A fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode PCIEX clock outputs.
19
BYPASS
Power
Pulldown
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.
LVCMOS/LVTTL interface levels.
20
VDDA
Power
Analog supply pin. Requires 24series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
K
K
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs Outputs
Inputs Outputs
FS0 PCIEX0
FS1 PCIEX1
0 5/4
01
11
1 5/4
TABLE 3C. BYPASS TABLE
Inputs
BYPASS
0
1
Mode
PLL Mode
Bypass Mode
(output = inputs)
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, NOE0
Inputs Outputs
nOE0
PCIEX0
0 Enabled
1 HiZ
TABLE 3E. OUTPUT ENABLE
FUNCTION TABLE, NOE1
Inputs Outputs
nOE1
PCIEX1
0 Enabled
1 HiZ
TABLE 3F. PLL BANDWIDTH TABLE
Inputs
Bandwidth
PLL_BW
0 500kHz
1 1MHz
9DB202CG
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2
REV. A OCTOBER 6, 2004

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ICS9DB202Two 0.7V current mode differential HCSL output pairsIntegrated Circuit Systems
Integrated Circuit Systems


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