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ICS954204 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Control HubTM for Mobile P4TM Systems - Integrated Circuit Systems

भाग संख्या ICS954204
समारोह Programmable Timing Control HubTM for Mobile P4TM Systems
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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ICS954204 pdf
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Integrated
Circuit
Systems, Inc.
ICS954204
Pin Description
PIN # PIN NAME
1 VDDPCI
2 GND
3 PCICLK3
4 PCICLK4
5 PCICLK5
6 GND
7 VDDPCI
8 ITP_EN/PCICLK_F0
9 *SELSRC_LCDCLK#/PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 FSLA/USB_48MHz
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FSLB/TEST_MODE
17 LCDCLK_SST/SRCCLKT0
18 LCDCLK_SSC/SRCCLKC0
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
PIN TYPE DESCRIPTION
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Latched input select for LCD_ss/ SRCCLK output frequency:
0 = LCD,
1 = SRCCLK/ 3.3V free-running PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of SRCCLK differential pair.
Selected by SEL_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of
SRCCLK differential pair. Selected by SEL_LCDCLK#
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
0933D—03/16/05
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