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ICS9FG108 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable FTG for Differential P4 CPU - Integrated Circuit Systems

भाग संख्या ICS9FG108
समारोह Programmable FTG for Differential P4 CPU
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS9FG108?> डेटा पत्रक पीडीएफ

ICS9FG108 pdf
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
Pin Description
PIN #
PIN NAME PIN TYPE
DESCRIPTION
1 XIN/CLKIN
IN Crystal input or Reference Clock input
2 X2
OUT Crystal output, Nominally 14.318MHz
3 VDD
PWR Power supply, nominal 3.3V
4 GND
PWR Ground pin.
5 REFOUT
OUT Reference Clock output
6 FS2
IN Frequency select pin.
7 OE_7**
IN
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
8 DIF_7
OUT 0.7V differential true clock output
9 DIF_7#
OUT 0.7V differential complement clock output
10 VDD
PWR Power supply, nominal 3.3V
11 DIF_6
OUT 0.7V differential true clock output
12 DIF_6#
OUT 0.7V differential complement clock output
13 OE_6*
Active high input for enabling output 6.
IN 0 = tri-state outputs, 1= enable outputs
14 VDD
PWR Power supply, nominal 3.3V
15 GND
PWR Ground pin.
16 OE_5*
IN Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
17 DIF_5
OUT 0.7V differential true clock output
18 DIF_5#
OUT 0.7V differential complement clock output
19 VDD
PWR Power supply, nominal 3.3V
20 DIF_4
OUT 0.7V differential true clock output
21 DIF_4#
OUT 0.7V differential complement clock output
22 OE_4**
IN
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
23 SDATA
I/O Data pin for SMBus circuitry, 5V tolerant.
24 SCLK
IN Clock pin of SMBus circuitry, 5V tolerant.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
ICS9FG108
0823E—04/13/06
2

विन्यास 17 पेज
डाउनलोड[ ICS9FG108 Datasheet.PDF ]


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अनुशंसा डेटापत्रक

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ICS9FG104Programmable FTG for Differential P4TM CPUIntegrated Circuit Systems
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