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ICS94229 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable System Clock Chip - Integrated Circuit Systems

भाग संख्या ICS94229
समारोह Programmable System Clock Chip
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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ICS94229 pdf
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ICS94229
Advance Information
Pin Descriptions
PIN NUMBER
1, 15, 23, 25,
2, 8, 12, 19,
29, 37, 43
3
4
5
6
7
9
10
21, 20, 18, 17,
16, 14, 13, 11
22
24
28, 27, 26
30
31
32
33
PIN NAME
VDD
GND
X1
X2
AVDD48
FS21, 2
48MHz
FS31, 2
24_48MHz
WDEN
PCICLK_F
SEL24_48#1, 2
PCICLK0
PCICLK (8:1)
PCICLK9_E
SRESET#1
AGP (2:0)
SCLK
SDATA
AGND
AVDD
34 PD#
35 PCI_STOP#
36 CPU_STOP#1, 2
38 CPUCLK_CSC0
39 CPUCLK_CST0
40 VDDL
42 CPUCLKT0
41 CPUCLKC0
44 AGP_STOP#
45 RATIO
46 REF_F
FS11, 2
47
REF1
FS01, 2
48
REF0
TYPE
PWR Power supply, nominal 3.3V
DESCRIPTION
PWR Ground
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
IN
OUT
Crystal input, has internal load cap (36pF) and feedback resistor from X2
Crystal output, nominally 14.318MHz. Has internal load cap (36pF)
Power supply, nominal 3.3V
Frequency select pin. Latched Input
48MHz output clock
Frequency select pin. Latched Input
24 or 48MHz clock output
Hardware enable of watch dog circuit. Default safe frequency is 100MHz.
Free running PCI clock not affected by PCI_STOP# for power management.
Logic input to select 24 or 48MHz for pin 7 output
PCI clock output
OUT PCI clock outputs.
OUT
OUT
OUT
IN
I/O
PWR
PWR
IN
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#.
Real time system reset signal for watchdog tmer timeout. This signal is active low.
AGP clock outputs
Clock input of I2C input, 5V tolerant input
Data pin for I2C circuitry 5V tolerant
Analog ground
Power supply, nominal 3.3V
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low
This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic "0"
level when driven low.
"Complementary" clock of differential pair CPU output. These push-pull outputs need an
external 1.5V pull-up (push-pull)
"True" clock of differential pair CPU output. These push-pull outputs need an external 1.5V
pull-up (push-pull).
Power supply for CPUCLKs, nominal 2.5V
"True" clock of differential pair CPU output. These open drain outputs need an external 1.5V
pull-up (open drain).
"Complementary" clock of differential pair CPU output. These open drain outputs need an
external 1.5V pull-up (open drain).
Stops all AGP clocks at logic 0 level, when input low
Outputs a "0" for 100MHz or "1" for 133MHz to the South Bridge
14.318 MHz free running reference clock., not afftected by REF_STOP#
Frequency select pin. Latched Input
14.318 MHz reference clock.
Frequency select pin. Latched Input
14.318 MHz reference clock.
Notes:
1w: wIwnte.rDnaal PtuallS-uhp eReestis4toUr o.fc1o2m0K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2

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