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ICS94215 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable System Clock Chip - Integrated Circuit Systems

भाग संख्या ICS94215
समारोह Programmable System Clock Chip
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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ICS94215
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,
33,39,45, 47
4
PIN NAME
VDD1
REF0
CPU_STOP#1, 2
GND
X1
5
6,14
7
8
10
11, 12, 13
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
X2
VDD2
PCICLK_F
MODE1, 2
FS31, 2
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK(2:4)
BUFFER IN
SDRAM (11:0)
VDD3
SDATA
SCLK
TYPE
PWR
OUT
IN
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the
STRONGER buffer for ISA BUS loads
This asynchronous input halts CPUCLKT, CPUCLKC & at logic
"0" level when driven low.
PWR Ground
IN
OUT
PWR
OUT
IN
IN
OUT
IN
OUT
OUT
IN
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Input to Fanout Buffers for SDRAM outputs.
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN
pin (controlled by chipset).
PWR Supply for SDRAM (0:12) nominal 3.3V.
IN Data input for I2C serial input, 5V tolerant input
IN Clock input of I2C input, 5V tolerant input
24_48MHz
OUT 24MHz/48MHz clock output
25
FS11, 2
IN Frequency select pin. Latched Input.
48MHz
26
FS01, 2
OUT 48MHz output clock
IN Frequency select pin. Latched Input
27 VDD4
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
40 SDRAM_OUT OUT Reference clock for SDRAM zero delay buffer
41 PD#1, 2
IN Powers down chip, active low
42 VDDCPU PWR Supply for CPU clock 3.3V
43
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
44
CPUCLKC0
OUT
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
46 CPUCLK
OUT 3.3V CPU clock output powered by pin 42
REF1
48 FS21, 2
OUT 14.318 MHz reference clock.
IN Frequency select pin. Latched Input
Notes:
1w: wIwnte.Drnaal tPauSll-hupeReets4isUto.rcoof m120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0442C—07/03/02
2

विन्यास 18 पेज
डाउनलोड[ ICS94215 Datasheet.PDF ]


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