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ICS94201 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable System Frequency Generator - Integrated Circuit Systems

भाग संख्या ICS94201
समारोह Programmable System Frequency Generator
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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ICS94201 pdf
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ICS94201
General Description
The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The ICS94201 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
Pin Configuration
PIN
N UM B ER
PIN NAM E
1, 9, 10, 18, 25,
32, 33, 37, 45
VDD
2 X1
3
4, 5, 14, 21,
28, 29, 36,
41, 49
8, 7, 6
11
12
X2
GND
3V66 [2:0]
PCICLK01
FS0
PCICLK11
FS1
TYPE
D ES CR IPTION
PWR
IN
OUT
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
13
20, 19, 17,
16, 15
SEL_24_48#
PCICLK21
PCICLK [7:3]
IN
OUT
OUT
22 PD#
IN
23 SCLK
IN
24 SDATA
OUT
FS3
34
48MHz
IN
OUT
35
38
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26
FS2
24_48MHz
SDRAM_F
SDRAM [11:0]
IN
OUT
OUT
OUT
50 GNDL
PWR
51, 52
CPUCLK [1:0] OUT
53, 55
VDDL
PWR
www54.DataISOAhPeICet4U.coOmUT
56
FS4
REF01
IN
OUT
Logic input to select output.
3.3V PCI clock output, with Synchronous CPUCLKs
3.3V PCI clock outputs, with Synchronous CPUCLKs
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
Clock input of I2C input
Data input for I2C serial input.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB
Logic input frequency select bit. Input latched at power on.
3.3V 24_48MHz output, selectable through pin 13, default is 24MHz.
3.3V SDRAM output can be turned off through I2C
3.3V output. All SDRAM outputs can be turned off through I2C
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. Output frequency derived from FS pins.
2.5V power suypply for CPU, IOAPIC
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
2

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डाउनलोड[ ICS94201 Datasheet.PDF ]


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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS94201Programmable System Frequency GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS94203Programmable System Frequency GeneratorIntegrated Circuit Systems
Integrated Circuit Systems


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