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ICS952001 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Preliminary Product Previes - Integrated Circuit Systems

भाग संख्या ICS952001
समारोह Preliminary Product Previes
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS952001?> डेटा पत्रक पीडीएफ

ICS952001 pdf
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General Description
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 11, 13, 19, 29,
42, 48
2
3
4
5, 8, 18, 24, 25,
32, 37, 41, 46
6
7
10, 9
PIN NAME
VDD
FS0
REF0
FS1
REF1
FS2
REF2
GND
X1
X2
ZCLK(1:0)
12 PCI_STOP#
14
15
23, 22, 21, 20, 17,
16
26
27
28, 36
30, 31
FS3
PCICLK_F0
FS4
PCICLK_F1
PCICLK (5:0)
MULTISEL
24_48MHz
48MHz
AVDD
AGPCLK (1:0)
PD#
33
Vtt_PWRGD
34 SDATA
35 SCLK
38 I REF
43, 39
44, 40
45
47
CPUCLKC (1:0)
CPUCLKT (1:0)
CPU_STOP#
SDRAM
TYPE
PWR
IN
OUT
IN
OUT
IN
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
OUT
IN
IN
I/O
IN
OUT
OUT
OUT
IN
OUT
DESCRIPTION
Power supply for 3.3V
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
PCI clock outputs.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
Analog power supply 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
SDRAM clock output.
Third party brands and names are the property of their respective owners.
2

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भाग संख्याविवरणविनिर्माण
ICS952001Preliminary Product PreviesIntegrated Circuit Systems
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