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M366S3323CT0-C1H डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - PC100 Unbuffered DIMM - Samsung semiconductor

भाग संख्या M366S3323CT0-C1H
समारोह PC100 Unbuffered DIMM
मैन्युफैक्चरर्स Samsung semiconductor 
लोगो Samsung semiconductor लोगो 
पूर्व दर्शन
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M366S3323CT0-C1H pdf
SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
M366S1724CT0-C1H/C1L
• Organization : 16Mx64
• Composition : 8Mx16 *8
• Used component part # : K4S281632C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
Contents ;
Byte #
Function Described
0 # of bytes written into serial memory at module manufacturer
1 Total # of bytes of SPD memory device
2 Fundamental memory type
3 # of row address on this assembly
4 # of column address on this assembly
5 # of module Rows on this assembly
6 Data width of this assembly
7 ...... Data width of this assembly
8 Voltage interface standard of this assembly
9 SDRAM cycle time @CAS latency of 3
10 SDRAM access time from clock @CAS latency of 3
11 DIMM configuration type
12 Refresh rate & type
13 Primary SDRAM width
14 Error checking SDRAM width
15 Minimum clock delay for back-to-back random column address
16 SDRAM device attributes : Burst lengths supported
17 SDRAM device attributes : # of banks on SDRAM device
18 SDRAM device attributes : CAS latency
19 SDRAM device attributes : CS latency
20 SDRAM device attributes : Write latency
21 SDRAM module attributes
22 SDRAM device attributes : General
23 SDRAM cycle time @CAS latency of 2
24 SDRAM access time from clock @CAS latency of 2
25 SDRAM cycle time @CAS latency of 1
26 SDRAM access time from clock @CAS latency of 1
27 Minimum row precharge time (=tRP)
28 Minimum row active to row active delay (tRRD)
29 Minimum RAS to CAS delay (=tRCD)
30 Minimum activate precharge time (=tRAS)
31 Module Row density
32 Command and address signal input setup time
33 Command and address signal input hold time
34 Data signal input setup time
Function Supported
-1H -1L
128bytes
256bytes (2K-bit)
SDRAM
12
9
2 Rows
64 bits
-
LVTTL
10ns
10ns
6ns 6ns
Non parity
15.625us, support self refresh
x16
None
tCCD = 1CLK
1, 2, 4, 8 & full page
4 banks
2&3
0 CLK
0 CLK
Non-buffered, non-registered
& redundant addressing
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
10ns
6ns
-
-
20ns
12ns
7ns
-
-
20ns
20ns
20ns
20ns
20ns
50ns
50ns
2 Rows of 64MB
2ns 2ns
1ns 1ns
2ns 2ns
Hex value
-1H -1L
80h
08h
04h
0Ch
09h
02h
40h
00h
01h
A0h A0h
60h 60h
00h
80h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
Note
1
1
2
2
0Eh
A0h C0h
60h 70h
00h 00h
00h 00h
14h 14h
14h 14h
14h 14h
32h 32h
10h
20h 20h
10h 10h
20h 20h
2
2
Rev 0.1 Apr. 2000

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