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ICS950410 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - AMD - K System Clock Chip - Integrated Circuit Systems

भाग संख्या ICS950410
समारोह AMD - K System Clock Chip
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS950410?> डेटा पत्रक पीडीएफ

ICS950410 pdf
ICS950410
Advance Information
Pin Descriptions
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1 ~*FS0/REF0
I/O Frequency select latch input pin / 14.318 MHz reference clock.
2 VDDHTT
3 X1
4 X2
5 GND
6 *ModeA/HTTCLK0
7 *ModeB/PCICLK8/HTTCLK1
8 PCICLK9/HTTCLK2
9 VDDPCI
10 GND
11 PCICLK11/HTTCLK3
12 *FS2/PCICLK10
13 PCICLK0
14 PCICLK1
15 GND
16 VDDPCI
17 PCICLK2
18 PCICLK3
19 VDDPCI
20 GND
21
2XPCICLK4
22 2XPCICLK5
23 2XPCICLK6
24 2XPCICLK7
25 SCLK
26 SDATA
27 24_48MHz/Sel24_48#*
28 AVDD48
29 GND
30 48MHz/FS3**
31 PD#*
32 Turbo#
33 GND
34 CPUCLK8C2
35 CPUCLK8T2
36 VDDCPU
37 GND
38 CPUCLK8C1
39 CPUCLK8T1
40 VDDCPU
41 CPUCLK8C0
42 CPUCLK8T0
43 GND
44 VDDA
45 Reset#
46 VDDREF
47 GND
48 REF1/FS1*
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
I/O
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
I/O
I/O
PWR
PWR
I/O
IN
IN
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
OUT
PWR
PWR
I/O
Supply for HTT clocks, nominal 3.3V.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Mode selection latch input pin / Hyper Transport output.
Mode selection latch input pin / PCI clock output / Hyper Transport output.
PCI clock output / Hyper Transport output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output / Hyper Transport output.
Frequency select latch input pin / 3.3V PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output. This output is default @ 2X drive and can be programmed to lower
drive via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower
drive via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower
drive via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower
drive via IIC.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
Ground pin.
Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal are stopped.
Real time input pin to change frequency to a pre-programmed under or over clock
entries located in IIC Rom table.
Ground pin.
Complimentary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Ground pin.
Complimentary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin.
3.3V power for the PLL core.
Real time system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
0888—04/06/04
2

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