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ICS950508 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Control Hub - Integrated Circuit Systems

भाग संख्या ICS950508
समारोह Programmable Timing Control Hub
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS950508?> डेटा पत्रक पीडीएफ

ICS950508 pdf
Integrated
Circuit
Systems, Inc.
ICS950508
General Description
The ICS950508 is a single chip clock solution for desktop designs using the 810/810E, 815 and 815 B-Step style chipset. It
provides all necessary clock signals for such a system.
The ICS950508 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN NUMBER
PIN NAME
1, 9, 10, 18, 25, 32, 33, 37, 45 VDD
2 X1
3
4, 5, 14, 21, 28, 29, 36,
41, 49
8, 7, 6
11
12
13
20, 19, 17, 16, 15
X2
GND
3V66 (2:0)
PCICLK01
FS0
PCICLK11
FS1
SEL_24_48#
PCICLK21
PCICLK (7:3)
PD#
22
Vtt_PWRGD
23 SCLK
24 SDATA
34
FS3
48MHz
FS2
35 24_48MHz
38
48, 46, 47, 44, 43, 42, 40, 39,
31, 30, 27, 26
50
SDRAM_F
SDRAM (11:0)
GNDL
51, 52
CPUCLK (1:0)
53, 55
54
56
VDDL
IOAPIC
FS4
REF01
0470E—04/06/05
TYPE
DESCRIPTION
PWR
IN
OUT
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback resistor
from X2
Crystal output, nominally 14.318MHz. Has internal load cap
(33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
PWR
OUT
PWR
OUT
IN
OUT
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
Logic input to select output.
3.3V PCI clock output, with Synchronous CPUCLKs
3.3V PCI clock outputs, with Synchronous CPUCLKs
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and
PD# signal. When Vtt_PWRGD goes high the frequency select
will be latched at power on; thereafter the pin is an asynchronous
active low power down pin.
Clock pin for I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB
Logic input frequency select bit. Input latched at power on.
3.3V 24_48MHz output, selectable through pin 13, default is
24MHz.
3.3V SDRAM output can be turned off through I2C
3.3V output. All SDRAM outputs can be turned off through I2C
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. Output frequency derived from FS
pins.
2.5V power suypply for CPU, IOAPIC
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
2

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