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ICS950901 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Control Hub - Integrated Circuit Systems

भाग संख्या ICS950901
समारोह Programmable Timing Control Hub
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS950901?> डेटा पत्रक पीडीएफ

ICS950901 pdf
Integrated
Circuit
Systems, Inc.
ICS950901
General Description
The ICS950901 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory.
with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all
the necessary clock signals for such a system.
The ICS950901 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1
2, 6, 16, 24, 38
4
5
7
PIN NAME
SEL24_48
REF
VDD
X1
X2
FS3
48MHz
8
3, 9, 13, 20, 25,
36, 44, 47
10
11
FS2
24_48MHz
GND
FS0
PCICLK_F
FS1
PCICLK0
22 PD#
21, 19, 18, 17, 15, 14 PCICLK (7:2)
27, 26, 23
AGP (2:0)
28 SCLK
29 SDATA
30 RESET#
33
34, 39
Vtt_PWRGD#
CPUCLKC_(1:0)
35, 40
37
41
42
43
45, 46
48
CPUCLKT_(1:0)
I REF
CPUCLKC_CS
CPUCLKT_CS
VDDCPU_CS (2.5V)
IOAPIC (1:0)
VDDAPIC (2.5V)
TYPE
DESCRIPTION
IN Selects either 24 or 48MHz output.
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply.
IN Crystal input, has internal load cap (33pF) and feedback resistor from X2.
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
IN Logic input frequency select bit. Input latched at power on.
OUT 3.3V Fixed 48MHz clock output..
IN Logic input frequency select bit. Input latched at power on.
OUT Selectable 24 or 48MHz output.
PWR Ground pins for 3.3V supply.
IN
OUT
IN
OUT
IN
OUT
OUT
IN
I/O
OUT
IN
OUT
OUT
OUT
OUT
OUT
PWR
OUT
PWR
Logic input frequency select bit. Input latched at power on.
3.3V Free running PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output.
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 3ms.
3.3V PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Clock pin for I2C circuitry 5V tolerant.
Data pin for I2C circuitry 5V tolerant.
Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active
low.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0) is valid and ready
to be sampled (active low).
"Complementory" clocks of differential pair CPU outputs. These are current outputs and external
resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and external resistors are
required for voltage bias.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Complementory"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
True"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
Power for CPUCLK_CS outputs 2.5V.
2.5V clock outputs
Power for APIC clocks 2.5V.
Third party brands and names are the property of their respective owners.
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS950901Programmable Timing Control HubIntegrated Circuit Systems
Integrated Circuit Systems
ICS950902Programmable Timing Control HubIntegrated Circuit Systems
Integrated Circuit Systems


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