DataSheet.in

ICS950104 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable System Clock Chip for PIII Processor - Integrated Circuit Systems

भाग संख्या ICS950104
समारोह Programmable System Clock Chip for PIII Processor
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS950104?> डेटा पत्रक पीडीएफ

ICS950104 pdf
ICS950104
Advance Information
Pin Descriptions
PIN NUMBER
PIN NAME
1 CPUCLKC0
2 CPUCLKT0
3, 9, 18, 30, 37
4, 12, 17, 25, 31,
36, 46, 48
5, 22
6
7
8
10
11
13
21, 20, 19, 16, 15,
14
23
24
26
VDD
GND
AVDD
X1
X2
FS02, 3
REF0
FS12, 3
REF1
REF2
FS21, 3
PCICLK_F
PCICLK(5:0)
MULTSEL2, 3
24_48MHz
FS32, 3
48MHz
SCLK
PD#1
27
VttPWRGD#
TYPE
OUT
OUT
PWR
PWR
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
IN
DESCRIPTION
"Complementary" clocks of differential pair CPU outputs. These clocks are 180°
out of phase with SDRAM clocks. These open drain outputs need an external
1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
Power supply pins, nominal 3.3V
Ground pins
Analog power supply for 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
14.318 MHz reference clock.
Frequency select pin.
Free running PCICLK not stoped by PCI_STOP#
PCI clock outputs.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Selectable 48 or 24MHz output
Frequency select pin.
48MHz output clock
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. This pin
will be activiated when
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS
and MULTISEL0 inputs are valid and are ready to be sampled (active low)
28
CPU_STOP#1
This asynchronous input halts CPU, SDRAM, and AGP clocks at logic "0" level
IN when driven low, the stop selection can be programmed through I2C.
29 PCI_STOP#1
32, 33, 34, 35, 38, SDRAM ( 7:0 )
39, 40, 41
42 SDRAM_STOP#1
43 SDATA
44 VDDL
IN
OUT
IN
IN
PWR
Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input
low
Data input for I2C serial input, 5V tolerant input
Power supply pins, nominal 2.5V
45
CPUCLK
OUT
2.5V CPU clock
This pin establishes the reference current for the CPUCLK pairs. This
47
I REF
OUT pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
3: Internal Pull-down resistor of 120K to GND on indicated inputs.
Third party brands and names are the property of their respective owners.
2

विन्यास 19 पेज
डाउनलोड[ ICS950104 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS950104Programmable System Clock Chip for PIII ProcessorIntegrated Circuit Systems
Integrated Circuit Systems


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English