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ICS950201 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Programmable Timing Control Hub for P4 - Integrated Circuit Systems

भाग संख्या ICS950201
समारोह Programmable Timing Control Hub for P4
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS950201?> डेटा पत्रक पीडीएफ

ICS950201 pdf
Integrated
Circuit
Systems, Inc.
ICS950201
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR 3.3V power supply
2
X1
X2 Crystal
Input
14.318MHz Crystal input
3
X2
X1 Crystal
Output
14.318MHz Crystal output
7, 6, 5
PCICLK_F (2:0)
OUT
Free running PCI clock not affected by PCI_STOP#
for power management.
4, 9, 15, 20, 27,
31, 36, 41, 47
GND
PWR Ground pins for 3.3V supply
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
OUT PCI clock outputs
24,23, 22, 21
3V66 (5:2)
OUT 66MHz reference clocks, from internal VCO
24
3V66_5
OUT 66MHz reference clock, from internal VCO
25 PD# IN Invokes power-down mode. Active Low.
This 3.3V LVTTL input is a level sensitive strobe used to
28
Vtt_PWRGD#
IN
determine when FS(2:0) and MULTISEL0 inputs are valid
and are ready to be sampled
(active low)
29
SDATA
I/O Data pin for I2C circuitry 5V tolerant
30
SCLK
IN Clock pin of I2C circuitry 5V tolerant
33
3V66_0
OUT 66MHz reference clocks, from internal VCO
34
PCI_STOP#
IN
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
3.3V output selectable through I2C to be 66MHz from internal VCO
35
3V66_1/VCH_CLK
OUT or
48MHz (non-SSC)
38
48MHz_DOT
OUT 48MHz output clock for DOT
39
48MHz_USB
OUT 48MHz output clock for USB
40 FS2 IN Special 3.3V input for Mode selection, cannot be logic 1
This pin establishes the reference current for the CPUCLK pairs.
, 42
I REF
OUT This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current.
43
MULTSEL0
IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs
44, 48, 51
CPUCLKC (2:0)
OUT
"Complementory" clocks of differential pair CPU outputs. These are
current outputs and external resistors are required for voltage bias.
45, 49, 52
CPUCLKT (2:0)
OUT
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
53
CPU_STOP#
IN Halts CPUCLK clocks at logic 0 level, when input low
55, 54
FS (1:0)
IN Frequency select pins
56
REF
OUT 14.318MHz reference clock.
Power Groups
(Analog)
(Digital)
VDDA = Analog Core PLL1
VDDREF = REF, Xtal
VDD48 = 48MHz, PLL
0460G—08/31/04
VDDPCI
VDD3V66
VDDCPU
2

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डाउनलोड[ ICS950201 Datasheet.PDF ]


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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS950201Programmable Timing Control Hub for P4Integrated Circuit Systems
Integrated Circuit Systems
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Integrated Circuit Systems


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