DataSheet.in

ICS950401 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - AMD - K8 System Clock Chip - Integrated Circuit Systems

भाग संख्या ICS950401
समारोह AMD - K8 System Clock Chip
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
1 Page
		
<?=ICS950401?> डेटा पत्रक पीडीएफ

ICS950401 pdf
ICS950401
Pin Descriptions
PIN PIN
PIN
#
NAME
TYPE
DESCRIPTION
1 *FS0/REF0
I/O Frequency select latch input pin / 14.318 MHz reference clock.
2 VDDREF
3 X1
PWR Ref, XTAL power supply, nominal 3.3V
IN Crystal input, Nominally 14.318MHz.
4 X2
5 GND
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin.
6 *PCI33/HT66SEL#
7 PCICLK33/HT66_0
IN Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,
IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
8 PCICLK33/HT66_1
9 VDDPCI
10 GND
IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
11 PCICLK33/HT66_2
12 NC
IN PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
NC No Connect
13 PCICLK0
14 PCICLK1
OUT PCI clock output.
OUT PCI clock output.
15 GND
16 VDDPCI
PWR Ground pin.
PWR Power supply for PCI clocks, nominal 3.3V
17 PCICLK2
18 PCICLK3
OUT PCI clock output.
OUT PCI clock output.
19 VDDPCI
20 GND
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
21 PCICLK4
22 PCICLK5
23 PCICLK_F
OUT
OUT
I/O
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
24 *PCI_STOP#
I/O
Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
25 SCLK
26 SDATA
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 5V tolerant.
27 GND
28 24_48MHz/Sel24_48#*
29 VDD
PWR
I/O
PWR
Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
Power supply, nominal 3.3V
30 GND
31 48MHz
PWR Ground pin.
OUT 48MHz clock output.
32 VDDA
33 GNDA
34 GND
PWR 3.3V power for the PLL core.
PWR Ground pin for the PLL core.
PWR Ground pin.
35 VDD
36 CPUCLKC1
37 CPUCLKT1
PWR
OUT
OUT
Power supply, nominal 3.3V
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
True clock of differential CPU outputs. Push-pull requires external termination.
38 VDDCPU
39 GND
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin.
40 CPUCLKC0
OUT
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
41 CPUCLKT0
42 GNDA
OUT True clock of differential CPU outputs. Push-pull requires external termination.
PWR Ground pin for the PLL core.
43 VDDA
44 SPREAD*
PWR 3.3V power for the PLL core.
IN
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
45 REF2/FS2*
46 VDDREF
I/O 14.318 MHz reference clock / Frequency select latch input pin.
PWR Ref, XTAL power supply, nominal 3.3V
47 GND
48 REF1/FS1*
PWR Ground pin.
I/O 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
0499C—11/01/04
2

विन्यास 14 पेज
डाउनलोड[ ICS950401 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
ICS950401AMD - K8 System Clock ChipIntegrated Circuit Systems
Integrated Circuit Systems
ICS950402AMD - K8 System Clock ChipIntegrated Circuit Systems
Integrated Circuit Systems


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English