7809LP डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - 16-Bit Latchup Protected Analog to Digital Converter - Maxwell Technologies

भाग संख्या 7809LP
समारोह 16-Bit Latchup Protected Analog to Digital Converter
मैन्युफैक्चरर्स Maxwell Technologies 
लोगो Maxwell Technologies लोगो 
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7809LP pdf
16-Bit Latchup Protected Analog to Digital Converter 7809LP
1 R1IN Analog Input.
2 AGND1 Analog Ground. Used internally as ground reference point.
3 R2IN Analog Input.
4 R3IN Analog Input.
5 CAP Reference Buffer Capacitor. 2.2 µ F tantalum to ground.
6 REF Reference Input/Output. 2.2 µ F tantalum capacitor to ground.
7 AGND2 Analog Ground.
8 SB/BTC Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be
output in a Straight Binary format. If LOW, data will be output in a Binary Two’s Complement
9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized
to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the
data from the previous conversion, along with 16 clock pulses output on DATACLK.
10 DGND Digital Ground.
11 LPBIT Built In test function of the latchup protection. Drive LOW during normal operation.
12 LPSTATUS Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is
active and output data is invalid.
13 VANA Analog Supply Input. Nominally 5V.
14 VDIG Digital Supply Input. Nominally 5V.
15 SYNC Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on
CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK.
16 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized
to this clock. If EXT/INT is LOW, DATACLK will transmit 16 pulses after each conversion, and
then remain LOW between conversions.
17 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the
level of SB/BTC. In the external clock mode, after 16-bits of data, the 7809LOPO will output the
level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid
on both the rising and falling edges of DATACLK, and between conversions DATA will stay at
the level of the TAG input when the conversion was started.
18 TAG Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data input on TAG will
be output on DATA with a delay of 16 DATACLK pulses as long as CS is LOW and R/C is
19 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the
hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission
of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with
CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the
transmission of data from the previous conversion.
20 CS Chip Select. Internally OR’ed with R/C.
01.11.05 Rev 7
All data sheets are subject to change without notice 2
©2005 Maxwell Technologies
All rights reserved.

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