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8Q1024K8SRAM डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - high-performance 1M byte (8Mbit) CMOS static RAM - Aeroflex Circuit Technology

भाग संख्या 8Q1024K8SRAM
समारोह high-performance 1M byte (8Mbit) CMOS static RAM
मैन्युफैक्चरर्स Aeroflex Circuit Technology 
लोगो Aeroflex Circuit Technology लोगो 
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8Q1024K8SRAM pdf
NC
NC
A0
A1
A2
A3
A4
E1
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W1
A5
A6
A7
A8
A9
W2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 NC
43 E2
42 NC
41 A18
40 A17
39 A16
38 A15
37 G
36 DQ7
35 DQ6
34 VSS
33 VDD
32 DQ5
31 DQ4
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
Figure 2. 25ns SRAM Pinout (44)
PIN NAMES
A(18:0)
DQ(7:0)
En
Wn
G
VD D
VSS
Address
Data Input/Output
Device Enable
WriteEnable
Output Enable
Power
Ground
Notes:
1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.
DEVICE OPERATION
Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die . Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
G Wn En I/O Mode Mode
X1 X
1 3-state
Standby
X 0 0 Data in Write
1
1
0 3-state
Read2
0 1 0 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) withEn and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified tAVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
8Q1024K8SRAMhigh-performance 1M byte (8Mbit) CMOS static RAMAeroflex Circuit Technology
Aeroflex Circuit Technology


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