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IDT74LVC125A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O - Integrated Device

भाग संख्या IDT74LVC125A
समारोह 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
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IDT74LVC125A pdf
IDT74LVC125A
3.3VCMOSQUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
IOK VI < 0 or VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SOIC/ SSOP/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6 pF
COUT
Output Capacitance VOUT = 0V
5.5
8
pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
xA
xY
Description
Output-Enable Inputs (Active LOW)
Data Inputs
3-State Outputs
FUNCTION TABLE (EACH BUFFER)(1)
Inputs
Outputs
xOE xA xY
L HH
L LL
H XZ
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT74LVC125A3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/OIntegrated Device
Integrated Device


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