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ICS93716YG-T डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Cost DDR Phase Lock Loop Clock Driver - Integrated Circuit Systems

भाग संख्या ICS93716YG-T
समारोह Low Cost DDR Phase Lock Loop Clock Driver
मैन्युफैक्चरर्स Integrated Circuit Systems 
लोगो Integrated Circuit Systems लोगो 
पूर्व दर्शन
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<?=ICS93716YG-T?> डेटा पत्रक पीडीएफ

ICS93716YG-T pdf
ICS9371 6
Pin Descriptions
PIN NUMBER
PIN NAME
6, 11, 15, 28 GND
27, 25, 16, 14, 5, 1 CLKC(5:0)
26, 24, 17, 13, 4, 2 CLKT(5:0)
3, 12, 23
VDD
7 SCLK
8 CLK_INT
9 CLK_INC
10 VDDA
18 FB_OUTC
19 FB_OUTT
20 FB_INT
21 FB_INC
22 SDATA
TYPE
DESCRIPTION
PWR Ground
OUT "Complementary" clocks of differential pair outputs.
OUT "True" Clock of differential pair outputs.
PWR Power supply 2.5V
IN Clock input of I2C input, 5V tolerant input
IN "True" reference clock input
IN "Complementary" reference clock input
PWR
OUT
OUT
IN
IN
IN
Analog power supply, 2.5V
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Data input for I2C serial input, 5V tolerant input
0420E—04/01/03
2

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भाग संख्याविवरणविनिर्माण
ICS93716YG-TLow Cost DDR Phase Lock Loop Clock DriverIntegrated Circuit Systems
Integrated Circuit Systems


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