# J112 डेटा पत्रक PDF( Datasheet डाउनलोड )

## डेटा पत्रक - JFET Chopper Transistor (N-Channel- Depletion) - Motorola Inc

 भाग संख्या J112 समारोह JFET Chopper Transistor (N-Channel- Depletion) मैन्युफैक्चरर्स Motorola Inc लोगो पूर्व दर्शन 1 Page ``` J112 TYPICAL SWITCHING CHARACTERISTICS 1000 500 200 100 RK = RD′ 50 TJ = 25°C VGS(off) = 7.0 V 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 Figure 1. Turn–On Delay Time 50 1000 500 200 RK = RD′ 100 50 TJ = 25°C VGS(off) = 7.0 V 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 2. Rise Time 20 30 50 1000 500 TJ = 25°C 200 VGS(off) = 7.0 V 100 50 RK = RD′ 20 10 RK = 0 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 Figure 3. Turn–Off Delay Time 50 1000 500 200 RK = RD′ 100 50 20 RK = 0 10 5.0 TJ = 25°C VGS(off) = 7.0 V 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 4. Fall Time 20 30 50 RGEN 50 Ω VGEN +VDD SET VDS(off) = 10 V INPUT RK RD RT RGG 50 Ω VGG 50 Ω OUTPUT INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 µs DUTY CYCLE ≤ 2.0% &RGG RK )RD(RT 50) Ȁ + ) )RD RD RT 50 Figure 5. Switching Time Test Circuit NOTE 1 The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn–on interval, Gate–Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R′D) and Drain–Source Resistance (rds). During the turn–off, this charge flow is reversed. Predicting turn–on time is somewhat difficult as the channel resistance rds is a function of the gate–source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn–on time is non–linear. During turn–off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data ``` विन्यास 4 पेज डाउनलोड [ J112 Datasheet.PDF ]

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