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IDT74FCT16601ET डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS - Integrated Device Technology

भाग संख्या IDT74FCT16601ET
समारोह FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT74FCT16601ET pdf
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 SO56-1 43
SO56-2
15 SO56-3 42
16 41
17 40
18 39
19 38
20 37
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
VTERM(2) Terminal Voltage with Respect to
GND
VTERM(3) Terminal Voltage with Respect to
GND
TSTG Storage Temperature
Max.
–0.5 to +7.0
–0.5 to
VCC +0.5
–65 to +150
Unit
V
V
°C
IOUT DC Output Current
–60 to +120 mA
NOTES:
3247 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
W2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
IECAPACITANCE (TA = +25°C, f = 1.0MHz)
VSymbol Parameter(1)
CIN Input
Conditions Typ.
VIN = 0V
3.5
ECapacitance
CI/O I/O
VOUT = 0V 3.5
Max.
6.0
8.0
Unit
pF
pF
RNOTE:
Capacitance
3247 lnk 04
P1. This parameter is measured at characterization but not tested.
A15 21
VCC 22
A16 23
A17 24
36 B15
35 VCC
34 B16
33 B17
T
C FUNCTION TABLE(1,4)
GND
A18
OEBA
25
26
27
U32 GND
31 B18
D30 CLKBA
CLKENAB OEAB
XH
XL
Inputs
LEAB
X
H
CLKAB
X
X
Outputs
AB
XZ
LL
LEBA
O28 29
SSOP/
CLKENBA
TSSOP/TVSOP
TOP VIEW
RPIN DESCRIPTION
3247 drw 02
Pin Names
OEAB
PDescription
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
X L H X HH
H L L X X B0(2)
L L L LL
L L L HH
L L L L X B0(2)
L L L H X B0(3)
NOTES:
3247 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEAB
A-to-B Latch Enable Input
LEBA and CLKBA.
2. Output level before the indicated steady-state input conditions were
LEBA
B-to-A Latch Enable Input
established.
CLKAB
A-to-B Clock Input
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
CLKBA
Ax
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB A to B Clock Enable Input
Z = High-impedance
↑ = LOW-to-HIGH Transition
CLKENBA B to A Clock Enable Input
3247 tbl 01
5.9 2

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IDT74FCT16601ETFAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTSIntegrated Device Technology
Integrated Device Technology


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