DataSheet.in

IDT72V205 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - FIFO memories - Integrated Device Technology

भाग संख्या IDT72V205
समारोह FIFO memories
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT72V205?> डेटा पत्रक पीडीएफ

IDT72V205 pdf
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DESCRIPTION (CONTINUED)
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO
is used in a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall-Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation,whichconsistsofactivating RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through mode (FWFT). The XI and XO pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
high-speed submicron CMOS technology.
PIN CONFIGURATIONS
PIN 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 Q14
47 Q13
46 GND
45 Q12
44 Q11
43 VCC
42 Q10
41 Q9
40 GND
39 Q8
38 Q7
37 Q6
36 Q5
35 GND
34 Q4
33 VCC
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
4294 drw 02
2

विन्यास 25 पेज
डाउनलोड[ IDT72V205 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT72V201FIFO memoriesIntegrated Device Technology
Integrated Device Technology
IDT72V205FIFO memoriesIntegrated Device Technology
Integrated Device Technology


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English